1. Field
Exemplary embodiments relate to a semiconductor device and a method of manufacturing the same, and a semiconductor package including the semiconductor device. More particularly, exemplary embodiments relate to a semiconductor device having a via structure and a method of manufacturing the same, and a semiconductor package including the semiconductor device.
2. Description of the Related Art
As semiconductor devices have been highly integrated, a three-dimensional packaging technology in which a plurality of chips may be stacked on each other has been developed. A through silicon via (TSV) technology is a packaging technology in which a via hole may be formed through a silicon substrate and a via electrode may be formed in the via hole.
In order to electrically connect a chip having a TSV therein to another chip, a conductive bump may be formed to contact the TSV, and a back side of a silicon substrate in which the TSV is formed may be partially removed and a chemical mechanical polishing (CMP) process may be performed to expose the TSV. However, when the CMP process is performed, the TSV adjacent to a scribe lane region may be bent or may fall down. Thus, a semiconductor device including the TSV and a semiconductor package including the semiconductor device may exhibit poor reliability.